As the dimensions of multilayer wiring array features continue to shrink, the fabrication of vias is becoming increasingly more difficult. Namely, conventional via fabrication processes are unable to keep up with currently desirable scaled feature sizes. FIGS. 1A-C, for example, illustrate common problems associated with conventional via fabrication processes, when smaller feature sizes (e.g., 45 nanometer (nm) node or smaller technology) are involved. As shown in FIG. 1A, dielectric layer 120 is deposited over substrate 100, and via 101 is etched into dielectric layer 120. As shown in FIG. 1B, via 101/surface of dielectric 120 are lined with diffusion barrier layer 130. The diffusion barrier layer can be tantalum nitride (TaN), or any other suitable diffusion barrier material. Electroplating is used to fill via 101 with copper (Cu). However, in order to perform the electroplating, it is first necessary to deposit a seed layer onto which the Cu can be subsequently plated. Namely, as shown in FIG. 1C, seed layer 140 is formed by sputter depositing Cu onto diffusion barrier layer 130.
A problem with this approach is that, as the via width shrinks to below about 80 nm and the aspect (depth/width) ratio becomes larger than about 5:1, the electroplating of the structure begins to fail. As shown in FIG. 1C, there is a substantial non-uniformity of the Cu thickness in seed layer 140. This non-uniformity is a consequence of the directional nature of the sputter deposition process coupled with the fact that a layer of Cu having a sufficient thickness so as to be continuous is required on the via bottom/sidewalls to ensure that there are no spots that cannot be plated. As a result, an excess amount of Cu is deposited on horizontal surfaces of the via. This excess Cu ends up overhanging the via opening. As a result, when electroplating is attempted this overhang occludes the via opening and causes the via opening to close off leaving an unfilled void within in the via, which is a catastrophic fault.
In an attempt to prevent the above-described overhang occlusion problem, an alternative approach has been devised where instead of sputter depositing a Cu seed layer onto the diffusion barrier layer, a ruthenium (Ru) seed layer is deposited onto the diffusion barrier layer by chemical vapor deposition (CVD), i.e., from a ruthenium carbonyl (Ru3(CO)12) precursor in the presence of excess CO. A Ru seed layer produced in this manner can be conformally deposited and thus does not create a thick overhanging layer, which greatly reduces the problem of void formation in the subsequent Cu electroplating step.
Use of a Ru seed layer, however, has significant drawbacks that arise from the relatively high resistivity of Ru compared to Cu and the chemical inertness of Ru. For example, following electroplating chemical-mechanical polishing (CMP) is typically used to plane the via metal down to the dielectric surface. As a practical matter, five nm is an approximate upper limit for the amount of Ru which can be polished away using a standard Cu polishing slurry. However, the bulk resistivity of Ru is more than four times higher than that of Cu. If only five nm of Ru are deposited, the resistivity of the resulting structure renders electroplating extremely difficult, as voltage drops across the wafer cause unacceptable non-uniformity in the Cu deposition. One could increase the conductivity of the substrate by depositing a thicker layer of Ru, and alleviate this problem, but then the subsequent CMP process would not be possible. One is left with a choice of problems, if the Ru is thick enough to make plating easy, subsequent CMP is not possible with the standard Cu polishing slurry. If the Ru layer is thinned to the point where CMP becomes possible, the substrate is too resistive for uniform plating using standard techniques. Furthermore, even if a method is developed to polish thicker layers of Ru, it would not be a desirable solution. The additional Ru added to facilitate the electroplating process would remain in the vias after CMP, which would reduce the volume available in the vias for Cu, and the resistance of the vias would be significantly increased, degrading performance.
Thus, improved via fabrication processes are needed that can accommodate the most current scaled technology requirements and can consistently produce properly functioning, viable vias.